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Micrel, Inc.
5V/3.3V 32-175Mbps AnyRate(R) SY87700V SY87700V CLOCK AND DATA RECOVERY Use lower-power SY87700AL for 3.3V systems
FEATURES
s 3.3V and 5V power supply options s SONET/SDH/ATM compatible s Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream, clock generation from 32Mbps to 175Mbps s Two on-chip PLLs: one for clock generation and another for clock recovery s Selectable reference frequencies s Differential PECL high-speed serial I/O s Line receiver input: no external buffering needed s Link Fault indication s 100K ECL compatible I/O s Complies with Bellcore, ITU/CCITT and ANSI specifications such as OC-1, OC-3, FDDI, Fast Ethernet, as well as proprietary applications s Available in 32-pin EPAD-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but not recommended for new designs, see page 2 for details)
AnyRate(R)
DESCRIPTION
The SY87700V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 175Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87700V also includes a link fault detection circuit. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
APPLICATIONS
s SONET/SDH/ATM OC-1/OC-3 s Fast Ethernet s Proprietary architectures up to 175Mbps
BLOCK DIAGRAM
PLLR P/N RDOUTP (PECL) RDOUTN
0 1 PHASE/ FREQUENCY DETECTOR LINK FAULT DETECTOR
RDINP (PECL) RDINN
PHASE DETECTOR
CHARGE PUMP
VCO
RCLKP (PECL) RCLKN
CD (PECL) REFCLK (TTL)
LFIN (TTL)
PHASE/ FREQUENCY DETECTOR
CHARGE PUMP
VCO
1 0
TCLKP (PECL) TCLKN
DIVIDER BY 8, 10, 16, 20
SY87700V
DIVSEL 1/2 (TTL) PLLS P/N FREQSEL 1/2/3 (TTL) CLKSEL (TTL)
VCC VCCA VCCO GND
AnyRate is a registered trademark of Micrel, Inc. M9999-073008 hbwhelp@micrel.com or (408) 955-1690
Rev.: L
Amendment: /0
1
Issue Date: July 2008
Micrel, Inc.
SY87700V
PACKAGE/ORDERING INFORMATION
VCCA 1 LFIN 2 DIVSEL1 3 RDINP 4 RDINN 5 FREQSEL1 6 REFCLK 7 FREQSEL2 8 FREQSEL3 9 N/C 10 PLLSP 11 PLLSN 12 GND 13 GND 14 Top View SOIC Z28-1 & S28-1 28 VCC 27 CD 26 DIVSEL2 25 RDOUTP 24 RDOUTN 23 VCCO 22 RCLKP 21 RCLKN 20 VCCO 19 TCLKP 18 TCLKN 17 CLKSEL 16 PLLRP 15 PLLRN
Ordering Information(1)
Part Number SY87700VZC(3, 4) SY87700VZCTR(2, 3, 4) SY87700VHC(3) SY87700VHCTR(2, 3) SY87700VZH(3, 4) Package Type Z28-1 Z28-1 H32-1 H32-1 Z28-1 Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Package Marking SY87700VZC SY87700VZC SY87700VHC SY87700VHC Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb
SY87700VZH with NiPdAu Pb-Free bar line indicator Pb-Free SY87700VZH with NiPdAu Pb-Free bar line indicator Pb-Free SY87700VHH with NiPdAu Pb-Free bar line indicator Pb-Free SY87700VHH with NiPdAu Pb-Free bar line indicator Pb-Free
SY87700VZHTR(2, 3, 4) Z28-1 SY87700VHH(3) SY87700VHHTR(2, 3) H32-1 H32-1
28-Pin SOIC (Z28-1)
32 NC RDINP RDINN FREQSEL1 REFCLK FREQSEL2 FREQSEL3 NC 1 2 3 4 5 6 7 8 9 PLLSP
31 30 29 28 27 26 25 24 RDOUTP 23 RDOUTN 22 VCCO Top View EPAD-TQFP H32-1 21 RCLKP 20 RCLKN 19 VCCO 18 TCLKP 17 TCLKN 10 11 12 13 14 15 16 PLLRN PLLSN GNDA GND PLLRP GND CLKSEL
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 4. For optimum reliability, care should be taken when using the Z28-1 SOIC package to maintain the package case temperature at or below 70C.
32-Pin EPAD TQFP (H32-1)
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DIVSEL1
DIVSEL2
VCCA
VCCA
LFIN
VCC
VCC
CD
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Micrel, Inc.
SY87700V
PIN DESCRIPTIONS
INPUTS RDINP, RDINN [Serial Data Input] Differential PECL. These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of five frequency ranges depending on the state of the FREQSEL pins. See "Frequency Selection" Table. REFCLK [Reference Clock] TTL Inputs. This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. CD [Carrier Detect] PECL Input. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs. These inputs select the output clock frequency range as shown in the "Frequency Selection" Table. DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs. These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the "Reference Frequency Selection" Table. CLKSEL [Clock Select] TTL Inputs. This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. OUTPUTS LFIN [Link Fault Indicator] TTL Output. This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. RDOUTP, RDOUTN [Receive Data Output] Differential PECL. These ECL 100K outputs (+3.3V or +5V referenced) represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. RCLKP, RCLKN [Clock Output] Differential PECL. These ECL 100K outputs (+3.3V or +5V referenced) represent the recovered clock used to sample the recovered data (RDOUT). TCLKP, TCLKN [Clock Output] Differential PECL. These ECL 100K outputs (+3.3V or +5V referenced) represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). PLLSP, PLLSN [Clock Synthesis PLL Loop Filter] External loop filter pins for the clock synthesis PLL. PLLRP, PLLRN [Clock Recovery PLL Loop Filter] External loop filter pins for the receiver PLL. POWER & GROUND VCC VCCA VCCO GND N/C
Note 1.
Supply Voltage(1) Analog Supply Voltage(1) Output Supply Voltage(1) Ground No Connect
VCC, VCCA, VCCO must be the same value.
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SY87700V
FUNCTIONAL DESCRIPTION
Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30s data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. Lock Detect The SY87700V contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active.
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SY87700V
CHARACTERISTICS
Performance The SY87700V PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs.
A
Jitter Transfer (dB) 0.1
Sinusoidal Input Jitter Amplitude (UI p-p)
15 1.5
-20dB/decade
-20dB/decade
-20dB/decade
-20
Acceptable Range
0.40 f0 f1 f2
Frequency
f4
ft
fc
Frequency
OC/STS-N Level 3
f0 (Hz) 10
f1 (Hz) 30
f2 (Hz) 300
f3 (kHz) 6.5
ft (kHz) 65
OC/STS-N Level 3
fc (kHz) 130
P (dB) 0.1
Figure 1. Input Jitter Tolerance
Figure 2. Jitter Transfer
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SY87700V
FREQUENCY SELECTION TABLE(1)
FREQSEL1 0 1 1 1 1 0 0
Note 1. Note 2. X is a DON'T CARE.
FREQSEL2 1 0 0 1 1 1 0
FREQSEL3 1 0 1 0 1 0 X(Note 2)
fVCO/fRCLK 6 8 12 16 24 -- --
fRCLK Data Rates (Mbps) 125 -175 94 - 157 63 - 104 47 - 78 32 - 52 undefined undefined
SY87700V operates from 32-175MHz. For higher speed applications, the SY87701V operates from 35-1250MHz.
REFERENCE FREQUENCY SELECTION
DIVSEL1 0 0 1 1 DIVSEL2 0 1 0 1 fRCLK/fREFCLK 8 10 16 20
LOOP FILTER COMPONENTS(1)
R5
C3
PLLSP
PLLSN
Wide Range
R5 = 350 C3 = 1.0F (X7R Dielectric)
R6
C4
PLLRP
PLLRN
Wide Range
R6 = 680 C4 = 1.0F (X7R Dielectric)
Note 1. Suggested Values. Values may vary for different applications.
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Micrel, Inc.
SY87700V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VIN IOUT Rating Power Supply Voltage Input Voltage Output Current - Continuous - Surge Tstore TA TC
Note 1.
Value -0.5 to +7.0 -0.5 to VCC 50 100 -65 to +150 0 to +85 0 to +70
Unit V V mA
Storage Temperature Operating Temperature Case Temperature
C C C
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability.
PACKAGE THERMAL DATA(1)
JA (C/W) by Velocity (LFPM)
Package(1, 2) 28-Pin 32-Pin
Note 1. Note 2. Note 3.
0 80 27.6
200 -- 22.6
500 -- 20.7
SOIC(1, 2) EP-TQFP(3)
Case temperature not to exceed 70C recommended for 28-pin SOIC. 28-pin SOIC package is NOT recommended for new designs. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details.
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SY87700V
DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5% or 5.0V 5%, TA = 0C to + 85C for 32-TQFP, TC = 0C to 70C for SOIC.
Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Min. 3.15 4.75 -- Typ. 3.3 5.0 170 Max. 3.45 5.25 230 Unit V V mA Condition
PECL 100K DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5% or 5.0V 5%, TA = 0C to + 85C.
Symbol VIH VIL VOH VOL IIL Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input LOW Current Min. VCC -1.165 VCC -1.810 VCC -1.075 VCC -1.860 0.5 Typ. -- -- -- -- -- Max. VCC -0.880 VCC -1.475 VCC -0.830 VCC -1.570 -- Unit V V V V A 50 to VCC -2V 50 to VCC -2V VIN = VIL(Min.) Condition
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5% or 5.0V 5%, TA = 0C to + 85C for 32-TQFP, TC = 0C to 70C for SOIC.
Symbol VIH VIL VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input LOW Current Output Short Circuit Current Min. 2.0 -- 2.0 -- -125 -- -300 -15 Typ. -- -- -- -- -- -- -- -- Max. VCC 0.8 -- 0.5 -- +100 -- -100 Unit V V V V A A A mA IOH = -0.4mA IOL = 4mA VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. VOUT = 0V (maximum 1sec) Condition
AC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5% or 5.0V 5%, TA = 0C to + 85C for 32-TQFP, TC = 0C to 70C for SOIC.
Symbol fVCO fVCO tACQ tCPWH tCPWL tir tODC tr tf tSKEW tDV tDH Parameter VCO Center Frequency VCO Center Freq. Tolerance Acquisition Lock Time REFCLK Pulse Width HIGH REFCLK Pulse Width LOW REFCLK Input Rise Time Output Duty Cycle (RCLK/TCLK) ECL Output Rise/Fall Time (20% to 80%) Recovered Clock Skew Data Valid Data Hold Min. 750 -- -- 4 4 -- 45 100 -200 1/(2xfRCLK) - 200 1/(2xfRCLK) - 200 Typ. -- 5 -- -- -- 0.5 -- -- -- -- -- Max. 1250 -- 15 -- -- 2 55 500 +200 -- -- Unit MHz % s ns ns ns % of UI ps ps ps ps 50 to VCC -2V Condition fREFCLK x Byte Rate Nominal
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SY87700V
TIMING WAVEFORMS
tCPWL tCPWH
REFCLK
tODC
tODC
RCLK
tSKEW tDV tDH
RDOUT
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SY87700V
32-PIN APPLICATION EXAMPLE
VCC
R13
LED D2
Q1 2N2222A R12
DIVSEL1
DIVSEL2
VCCA
VCCA
LFIN
VCC
VCC
VEE
DIODE D1
CD
32
31
30
29
28
27
26
25 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN
VCC
1N4148
R3 R4 R5 R6 R7 R8 R9
NC
R10
1 2 3 4 5 6 7 8 9
PLLSP
24 23 22 21 20 19 18 17 10
PLLSN
RDINP RDINN FREQSEL1 REFCLK FREQSEL2 CLKSEL DIVSEL1 DIVSEL2 CD FREQSEL3 NC
1 2 3 4 5 6 7
11
VEEA
12
VEE
13
VEE
14
PLLRN
15
PLLRP
16
CLKSEL
VEE
R11 1k
SW1
C3
C4
GND
Ferrite Bead BLM21A102
R1 C1 C2
R2
VCC
VCCO (+2V) VCC (+2V) VCCA (+2V)
L3 L2 C5 22 F L1 C6 0.1 F C7 6.8 F C8 6.8 F C11 0.1 F C9 6.8 F C13 0.1 F
C12 0.01 F C15 0.1 F
C14 0.01 F
C16 0.01 F
GND
C10 6.8 F C17 0.1 F C18 0.01 F VEE (--3V)
VEE
C19 1.0 F C20 0.1 F C21 0.01 F
VEEA (--3V)
Note: C3, C4 are optional
C1 = C2 = 1.0F R1 = 350 R2 = 680 R3 through R10 = 5k R12 = 12k R13 = 130
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SY87700V
28-PIN APPLICATION EXAMPLE
GND SW1
VCC
1 2 3 4 5 6 (R17 - R22) 5k x 6
R8 130
LED D2
Ferrite Bead BLM21A102
VCC
Stand Off
0.1 F
FB1
C9
22 F
0.1 F
C8 C7
22 F
C6
GND Capacitor Pads (1206 format)
R1 C1
1 VCC
R2
VCCA
VCC 28 CD 27 DIVSEL2 26 RDOUTP 25 RDOUTN 24 VCCO 23 RCLKP 22 RCLKN 21 VCCO 20 TCLKP 19 TCLKN 18 CLKSEL 17
R6 R7 1k
J1 VCC 0.1 F 0.1 F
C14 C15
2 LFIN 3 DIVSEL1 4 RDINP 5 RDINN
Diode D1 1N4148
RDIN
C2 R3 R4
6 FREQSEL1 7 REFCLK 8 FREQSEL2 9 FREQSEL3 10 N/C 80
R5
See Table 1 GND
0.1 F 0.1 F
C16 C17
0.1 F 0.1 F
C18 C19
LOOP FILTER NETWORK
11 PLLSP 12 PLLSN 13 GND 14 GND
C3
1.5 F
50
C4
PLLRP 16 1.0 F
R11 R12 R13 R14 R15 R16
If VCC = +5V: R9 through R14 = 330 If VCC = +3.3V: R9 through R14 = 220
VCC
C5
PLLRN 15
REFCLK (TTL) NC
DPDT Slide Switch
GND
XTAL Oscillator 14 0.1 F
C13
Pin 1 (VCCA) 0.1 F Pin 28 (VCC) 0.1 F Pin 23 (VCCO) 0.1 F Pin 20 (VCCO) 0.1 F
C10
1
C11
VCC 120
R21
8
7
C12
Note 1.
C5 and C10-C12 are decoupling capacitors and should be kept as close to the power pins as possible.
For AC-Coupling Only
For DC Mode Only
when VCC = +5V
C1 = C2 = 0.1F R1 = R2 = 1.2k R3 = R4 = 3.4k
Table 1.
when VCC = +3.3V
C1 = C2 = 0.1F R1 = R2 = 680 R3 = R4 = 1k
when VCC = +5V
C1 = C2 = Shorted R1 = R2 = 82 R3 = R4 = 130
when VCC = +3.3V
C1 = C2 = Shorted R1 = R2 = 130 R3 = R4 = 82
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SY87700V
BILL OF MATERIALS (32-PIN EPAD-TQFP)
Item C1, C2 C3, C4 C5 C6 C7, C8, C9, C10 C19 C11, C13 C15, C17 C20 C12, C14 C16, C18 C21 D1 D2 J1, J2, J3, J4, J5 J6, J7, J8, J9, J10, J11, J12 L1, L2, L3 Q1 R1 R2 R3, R4, R5, R6 R7, R8, R9, R10 R11 R12 R13 SW1 206-7 CTS Part Number VJ0603Y105JXJAT VJ0603Y105JXJAT ECS-T1ED226R ECU-V1H104KBW ECS-T1EC685R ECJ-3YB1E105K ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW ECU-V1H103KBW ECU-V1H103KBW ECU-V1H103KBW 1N4148 P300-ND/P301-ND 142-0701-851 Panasonic Johnson Components Murata NTE Manufacturer Vishay Vishay Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Description 1.0F Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Critical 1.0F Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Optional 22F Tantalum Electrolytic Capacitor, Size D 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, Power Supply Decoupling 6.8F Tantalum Electrolytic Capacitor, Size C 1.0F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling Diode T-1 3/4 Red LED Gold Plated, Jack, SMA, PCB Mount Qty. 2 2 1 1 4 1 1 1 1 1 1 1 1 1 12
BLM21A102F NTE123A
Ferrite Beads, Power Noise Suppression 2N2222A Buffer/Driver Transistor, NPN 350 Resistor, 2%, Size 0402 Loop Filter Component, Critical 680 Resistor, 2%, Size 0402 Loop Filter Component, Critical 5k Pullup Resistors, 2%, Size 1206 1k Pulldown Resistor, 2%, Size 1206 12k Resistor, 2%, Size 1206 130 Pullup Resistor, 2%, Size 1206 SPST, Gold Finish, Sealed Dip Switch
3 1 1 1 8 1 1 1 1
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SY87700V
28 LEAD SOIC .300" WIDE (Z28-1)
Rev. 02
Note: The 28 Lead SOIC package is NOT recommended for new designs.
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SY87700V
32 LEAD EPAD TQFP (DIE UP) (H32-1)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 32-Pin EPAD-TQFP Package
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SY87700V
APPENDIX A
Layout and General Suggestions 1. 2. 3. 4. 5. 6. 7. 8. Establish controlled impedance stripline, microstrip, or co-planar construction techniques. Signal paths should have, approximately, the same width as the device pads. All differential paths are critical timing paths, where skew should be matched to within 10ps. Signal trace impedance should not vary more than 5%. If in doubt, perform TDR analysis of all high-speed signal traces. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1k resistor to VEE.
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+ 1 (408) 944-0800
FAX
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The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-073008 hbwhelp@micrel.com or (408) 955-1690
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